The present invention relates to an MIS transistor with self-aligned gate and its manufacturing method. An MIS transistor refers to a structure of Metal-Insulator-Semiconductor type such as, for example, that of MOS transistors (Metal-Oxide-Semiconductor).
In particular the invention relates to the manufacture, on a silicon substrate, of such transistors, capable of functioning in the ultra-high frequency ranges.
The invention can be applied to micro-electronics for manufacturing ultra-high frequency and/or power circuits, for example for producing circuits which can be used in the domain of telecommunications.
It is known that the components and circuits of the ultra-high frequency type are usually produced on substrates in gallium arsenide (GaAs) or on silicon substrates (Si).
For cost reasons, the circuits produced on gallium arsenide substrates are in general not very complex and do not have a high density of integration. The architecture of these circuits is thus not optimised from the point of view of their compactness.
Document [1] whose references are given at the end of the present description, concerns a method for manufacturing an MIS transistor with self-aligned gate on its source and drain regions.
This method relies on a stage of setting a sacrificial dummy gate for defining the placing of a source region, of a drain region, and the setting of a so-called definitive gate. The implementation of a dummy gate makes it possible to free the definitive gate from thermal treatments linked to the formation of the source and drain regions.
Furthermore, the method of document (1) enables the manufacture of a compact transistor, in particular reducing the contact guard relative to the interconnections made at the gate level.
During continuing research on raising the density of integration of components and circuits, one aim is to reduce the individual size of transistors and more particularly the size of their gate.
When the size of the gate is reduced, there are problems of adjustment of the threshold voltage of transistors and problems of drilling between drain and source.
A rise in the doping density of the channel region located under the gate makes it possible to adjust the threshold voltage and to raise the immunity to drilling between the source and drain zones.
However, the rise in the doping density under the gate is accompanied by a rise in parasite capacities existing between the source and channel on the one hand, and between the drain and channel on the other; and the mobility of the charge carriers is thus reduced.
When the dimensions of the gate are reduced, the doping increases in the channel and it become more difficult to optimise the frequency performances of the components. One of the limitations of frequency performance is the channel-source or channel-drain parasite capacity.
A description of the state of the art is also given in documents [3] and [4] whose references are provided after the description.
An aim of the present invention is to propose an MIS transistor and its manufacturing method which does not have the limitations mentioned above.
A particular aim of the present invention is to propose such a transistor which can be produced with especially reduced dimensions while still possessing good immunity to drilling.
A further aim of the invention is to be able to adjust the threshold voltage Vt of the transistor to a required value, chosen in function of the supply voltage.
A final aim of the invention is to propose a transistor with low parasite capacities and able to operate at high frequencies.
In order to achieve these aims, the Invention has more precisely the aim of a method for manufacturing an MIS transistor on a semiconductor substrate. The method comprises the following successive stages:
a) formation on the substrate of a layer, called the pedestal layer and, on this layer, formation of a sacrificial dummy gate, the dummy gate being set above a region of the substrate called the channel region.
b) formation in the substrate of source and drain regions, self-aligned on the dummy gate and defining at least partly the channel region,
c1) lateral coating of the dummy gate with at least one electrical insulation substance and elimination of the dummy gate to obtain a well above the channel region
c2) formation of spacers on the sides of the well,
c3) doping of a part of the channel region by ionic implantation in the well, using the spacers as implantation mask,
d) formation of a gate in the well, called the definitive gate, separated frown the substrate by a gate insulator layer.
According to the invention, the formation of the definitive gate is preceded by the elimination of at least a part of the pedestal layer located at the bottom of the well and at least a part of the pedestal layer extending under the spacers of the sides of the well, in order to form in this layer at least one recess over a part of the source and drain regions, the definitive gate extending into said space.
Thanks to the spacers equipping the sides of the well, and which are used as implantation mask, the doping of the channel is limited to a central part of the channel without reaching the source and drain regions.
This property makes it possible to adjust the threshold voltage of the transistor, by controlling the doping. It also makes it possible to raise the immunity of the transistor to a drain-source drilling, and above all to reduce the parasite capacities between the channel and the source and drain regions.
It should be noted that the doping stage c3 does not exclude using a substrate which is initially doped. In this case, the doping operation simply leads to a rise in the concentration or modification of the type or profile of doping in the central part of the channel.
Furthermore, thanks to the partial elimination of the pedestal layer under the spacers, the gate extends partly over the source and drain regions. When the source and drain are doped gradually, that is to say with a weakly doped zone turned towards the channel and a more highly doped zone turned away from the channel respectively, the edges of the gate extend as far as above the weakly doped zones. Such an architecture makes it possible to produce a good compromise between reduction of the resistance of access to the channel and reduction of channel-source and channel-drain parasite capacities.
The extension of the overlap of the gate above the weakly doped zones can, for example, be between 0 (when the edge of the gate arrives at the limit of a weakly doped zone) and half the width of the weakly doped zones.
According to a specially advantageous embodiment of the invention, the method can further comprise, before the end of the doping stage c3, the formation of a layer of oxide on the spacers. When these spacers formed on the sides of the well are made of a substance capable of being oxidised, the layer of oxide is preferably formed by oxidation of the spacers.
The aim of the oxide layer is not only to increase the thickness of the spacers on the sides of the well but also to control this thickness precisely in such a way as to define a very thin doped zone at the centre of the channel.
In fact, the extension of the doping zone in the channel depends on the free distance between the surfaces of the facing spacers.
By controlling the extension of the zone in this way, by oxidation of the spacers, it is possible to adjust the threshold voltage Vt of the transistor precisely.
The voltage Vt is chosen such that Vt less than Vs/3 for example, where Vs is the supply voltage of the transistor.
According to another preferred embodiment, one can form a dummy gate on a layer, called the pedestal layer, covering the surface of the substrate. Thus one eliminates part of the pedestal layer located at the bottom of the well, before the formation of said definitive gate.
When there is total or partial elimination of the pedestal layer in the well, the lateral spacers formed on the sides of the well also have the function of protecting these sides and in this way avoiding any widening of the well, which would prejudice the compactness of the transistor.
As mentioned above, elimination of the pedestal layer at the bottom of the well can advantageously comprise elimination of at least a part of the pedestal layer extending under the spacers of the sides of the well to form at least one recess over a part of the source and drain regions. The definitive gate which is finally formed then extends into this recess.
Furthermore, the method according to the invention can comprise, before formation of the definitive gate, elimination of the pedestal layer at the bottom of the well and the formation of a layer for insulating the gate.
Since the gate oxide formed at the bottom of the well has a lower thickness than that of the oxide of the pedestal layer, one obtains in fine, a gate with a cross section of an upside-down T.
It can be seen that when the spacers of the lateral sides of the well are oxidised, their superficial oxide layer is also eliminated or breached at the time of elimination (de-oxidisation) of the pedestal layer at the bottom of the well.
Thus, after this stage, and before putting the definitive gate into place, one can form a new oxide layer on the spacers. This measure makes it possible to adjust or exaggerate the upside-down T shape of the gate.
A further aim of the invention is an MIS transistor comprising a channel region in a substrate, as well as source and drain regions arranged on each side of the channel, and a gate set closely above the channel region. According to the invention, the channel has a doped central part between the source and drain regions, and separate from said source and drain regions.
When the channel can be doped overall or on the contrary doped unintentionally, one means by doped central part a part with doping at a higher concentration than the average doping concentration of the channel.
The doping can thus be adjusted, under the gate.
Furthermore, this central part is considered to be separate from the source and drain regions, meaning that a less doped zone or unintentionally doped zone is located respectively between the central part (doped) and each of the source and drain regions.
According to another embodiment, the gate can have a T-shaped cross-section (upside-down) with part of it forming the horizontal bar of the T turned towards the channel and extending partially over the source and drain regions.
Other properties and advantages of the present invention will become clearer by reading the following description, with reference to the drawings in the figures in the appendix. This description is given as a purely illustrative and non-limiting example.